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TI introduces industry's first 16-bit, dual-channel DAC family with 1 Gbps LVDS inputs

Wideband converter in ultra-small package maximizes carrier placement flexibility

Mar 31, 2008

DALLAS (March 31, 2008) - Texas Instruments Incorporated (TI) (NYSE: TXN) today introduced a high-performance 16-bit, dual channel, 1 GSPS (giga sample per second) digital-to-analog converter (DAC) family. The new single and dual-channel DAC family features a low-voltage differential signaling (LVDS) data input port at 1 Gbps, providing up to 400 MHz signal bandwidth. In addition, the DAC family offers flexible configuration options as well as industry-leading tools and support to ease design and speed time to market for base stations, wideband IF transmitters, radar, and test and measurement equipment. (See www.ti.com/dac5682Z-pr.)

Best-in-class performance and flexibility in a space-saving package

Offered in a small 9 mm x 9 mm QFN package, the DAC568x family builds upon TI's commitment to offer high-performance, integrated solutions by providing a 70 percent space savings over traditional data converters. The devices provide several configuration options to support different transmit architectures, such as direct up-conversion, real or complex IF, and different wireless air interfaces such as WCDMA, TD-SCDMA, WiMAX and LTE. For an output frequency of 160 Mhz, the devices achieve 73 dB ACPR for a single-carrier WCDMA application or 67 dBc for a four-carrier application. Along with the single-channel DAC5681 and DAC5681Z, the dual DAC5682Z offers many digitally configurable features such as:

  • Selectable low-, high-, or bypass filter modes
  • Interpolation: 2x, 4x or bypass
  • Optional +/-Fs/4 or +/-Fs/8 coarse mixer
  • Optional 2x-32x clock multiplying PLL
  • 8 sample input data FIFO

World-class tools and support reduce development time

TI also offers a complete suite of easy-to-use evaluation modules (EVMs) to allow designers to make rapid systems-level evaluation with the DAC5682ZEVM for baseband outputs and the TSW3082 for RF output. In addition, across its complete DAC portfolio, TI offers the TSW3100 digital pattern generator. The tool provides inputs to either evaluation platform via a 1 GSPS LVDS bus with up to 256 mega vector pattern depths. Together, the evaluation modules and TSW3100 provide a quick and cost-effective evaluation solution and allow designers to fully realize the increased system performance provided by the family's wide bandwidth, including the following:

  • Improved power amplifier linearization for digital pre-distortion (DPD) solutions with TI's GC5322 single-chip transmit processor solution
  • Enhanced resolution for radar and advanced imaging
  • Reduced cost of infrastructure, covering wide bandwidth with one implementation
  • Implementation of more standards in software-defined radios
  • Advanced system performance for test and measurement
To further simplify design, TI offers a wide variety of devices to complete the signal chain, including operational amplifiers (OPA695), a clock synchronizer and jitter cleaner (CDCM7005), an integrated PLL/VCO (TRF3761), and quadrature modulators (TRF3703). The DAC5682Z also works with TI's family of single- and multi-core wireless infrastructure-optimized digital signal processors.

Pricing and availability

The DAC5682Z is available now in a 64-pin quad flat no-lead (QFN) package and is priced at $31.95 each in 1,000-piece quantities (suggested resale pricing). Samples and EVMs for the entire 16-bit, 1 GSPS DAC family is available from www.ti.com/dataconverters.