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TI Introduces LVDS Serializer/Deserializer in Space-Saving Package

Feb 23, 2006

DALLAS (Feb. 23, 2006) - Texas Instruments (TI) introduced today low voltage differential signaling (LVDS) serializer and deserializer (SerDes) devices in a 5 mm x 5 mm QFN package. At less than 1/3 the size of competing devices, the TI chips save board space in a wide variety of applications including wireless base stations, data communications backplanes, and industrial and video systems, including in-vehicle infotainment and video. (See: www.ti.com/sc06043.)

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit SerDes chipset designed to transmit and receive serial data over LVDS differential backplanes at an equivalent parallel word clock rate in the range from 10 MHz to 66 MHz. This corresponds to a throughput range of 100Mbps to 660Mbps.

Key Features

  • 100-Mbps to 660-Mbps serial LVDS data payload bandwidth at 10-MHz to 66-MHz system clock 
  • Chipset (serializer/deserializer) power consumption less than 450 mW (typical) at 66 MHz 
  • Synchronization mode for faster lock 
  • Lock indicator 
  • No external components required for phase-locked loop
  • Qualified for industrial temperature range from -40°C to 85°C 
  • Programmable edge trigger on clock 
  • Flow-through pinout for easy printed circuit board layout

Availability and Pricing

The SN65LV1023A and SN65LV1224B are available today in volume in a 5 mm x 5 mm, 32-pin quad flat no-leads (QFN) package from TI and its authorized distributors. The devices are also available in a 28-pin small-scale outline package (SSOP). Suggested pricing in quantities of 1,000 is $4.60.
For an overview of interface products available from TI, please see the Interface Selection Guide available at interface.ti.com.