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TI Announces Programmable, Flexible Clock Multiplier that Delivers 3x Better Jitter Performance

Flexible Output Options Minimize Electromagnetic Interference

Oct 20, 2005

DALLAS (October 20, 2005) - Texas Instruments (TI) (NYSE: TXN) today announced a clock multiplier that integrates three on-chip phase locked loop (PLL) components to provide industry-leading flexibility and performance, including cutting period jitter by up to 70 percent compared to existing solutions and minimizing electromagnetic interference (EMI). Each of the device's six outputs can be programmed in-circuit or during operation for any clock frequency up to 300 MHz. This flexibility eases the design process, saves system cost and maximizes designers' ability to meet emerging standards in high-performance communications applications such as wireless base stations and telecommunications or data communications equipment. (See www.ti.com/sc05225.) 

Developed in TI's radio frequency (RF) Silicon-Germanium process, the three PLLs of the CDCE706 can accept a crystal, LVCMOS or differential input and generate six clocks from a single clock source. Using on-chip EEPROM technology, designers can easily program and save the device's register settings in non-volatile memory so that no re-programming is required at power-up. Designers can also use the 2-wire SMBus interface to dynamically reprogram the outputs as needed while the device is in the system.
The CDCE706 enables fast time-to-market by easing the design process while providing very low period jitter of less than 60 psec. The user only needs to define the input and output frequencies or the divider setting, which automatically sets the PLL parameters. This in turn guarantees high loop stability and frees the user from manually setting the charge-pump current, filter components, phase margin or loop bandwidth. TI's RF process technology allows integration of such features while maintaining excellent PLL frequency isolation.
In addition, the new device features very flexible output settings such as enable, disable, low-state, signal inversion, slew-rate control of 0.6 ns to 3.3 ns, and variable output supply voltage of 2.3 V to 3.6 V. Along with programmable spread spectrum clocking (SSC), these features provide designers a powerful tool to optimize their designs for the lowest electromagnetic interference (EMI). Also, the device's high-resolution PLL dividers enable zero parts per million (PPM) output clock error for high frequency stability.

Available Today

The CDCE706 is sampling today and will be in full production in 1Q2006. Suggested resale pricing is $3.60 each in 1,000-unit quantities. A development kit and programming kit will be available to simplify PLL design and programming. The CDCE706 will also be available in factory-programmed versions for high-volume applications. The device is 3.3 V supplied, operates in the industrial temperature range of -40C to 85C and is packed in a 20-pin thin shrink small outline package (TSSOP) package.


TI's high-performance analog products and digital signal processors (DSP) optimized for wireless infrastructure applications comprise the industry's most complete signal chain solution for base station OEMs. In addition to the

CDCE706

, TI offers other high-performance analog products and DSPs, including the

TMS320TCI6482

DSP. Nine of the top 10 base station OEMs use TI technology.


For information on TI's complete line of clock products for communications, consumer and memory applications, please see the Clocks and Timing Selection Guide at 

www.ti.com/clocks

.