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New Texas Instruments TMS320C6455 DSP Offers Incredible System Performance Gain Due to 2x-12x Boosts in Performance and I/O Bandwidth

The C6455 DSP Brings Serial RapidIO(R) and 2MB of Memory to Infrastructure Video, Telecom and Imaging Customers

May 16, 2005

HOUSTON (May 16, 2005) – Building on its leadership in high-performance signal processing, Texas Instruments [NYSE: TXN] (TI) today announced the TMS320C6455 digital signal processor (DSP), offering improved performance, reduced code size plus more on-chip memory and high bandwidth integrated peripherals including the Serial RapidIO® bus for inter-processor communications. Using the new C6455 DSP, developers of telecommunications, network and video infrastructure end-equipments and high-end imaging systems will see a system performance gain due to 2x -12x boosts in performance and I/O bandwidth, allowing them to integrate more high-bandwidth channels, achieve higher image definition, and produce more efficient software easily for faster time-to-market. For more information, please see: www.ti.com/c6455dsppr.

"The C6455 from TI supports our strategy for next generation DSP modules by enabling a step up in system performance for infrastructure applications requiring multiple DSPs per board while preserving our software investment," said Paul Virgo, director BPO marketing, Motorola Embedded Communications Computing. "By combining low power per channel, delivered by the 90nm process technology, with an easy to implement Gigabit Ethernet infrastructure, the C6455 will allow us to enhance our range of building blocks and Application-Enabling Platforms."


A High Data Bandwidth Device Architecture

The new C6455 DSP, 100 percent code compatible with previous TMS320C64x™ devices, incorporates Serial RapidIO and other new high bandwidth peripherals. New peripherals and features of this chip, as compared to previous 1 GHz C64x™ DSPs, include:

  • Serial RapidIO, featuring up to 25 Gbits/sec interconnectivity, enabling high performance multi-processing that is 12 times faster than previous external memory interfaces;
  • Gigabit Ethernet MAC (Memory Access Controller) offering 10 times more Ethernet bandwidth than previous C64x devices;
  • DDR2 (Double Data Rate) external memory interface delivering twice the throughput of currently available devices;
  • 66 MHz PCI (Peripheral Component Interconnect) bus interface providing twice the frequency of previous processors;
  • 2 MBytes of L2 Memory giving OEMs twice the amount of memory as previous C64x devices.


Serial RapidIO Offers Increased Bandwidth for HD Video and Telecom Infrastructure

The C6455 DSP’s integrated industry-standard Serial RapidIO bus decreases overall system cost by reducing the need for additional devices used for switching and processor aggregation. Supported by an industry association of leading device, system and software manufacturers, the Serial RapidIO interconnect enables high-speed, packet-switched peer-to-peer connectivity. Serial RapidIO thus makes it much easier to implement multi-processing, providing a performance breakthrough for multi-channel implementations on multiple processors. For video infrastructure applications, a 1x link is fast enough to send high-definition (HD) 1080i raw video between devices and a 4x link can easily send HD 1080p raw video between devices with bandwidth to spare. The use of Serial RapidIO in infrastructure applications with large “DSP farms” will allow the reduction of system cost (device count, board size and/or device cost) for OEM customers.


New C64x+ Core: More Performance, Smaller Code Size and 100% Code Compatible

The enhanced C64x+ DSP core on which the C6455 DSP is based adds new specialized instructions that on average, make code 20 to 30 percent more compact and 20 percent more cycle efficient than code based on TI’s current advanced C64x DSP architecture. The new instructions include complex and 32-bit wide multiplications and simultaneous add/subtract instructions, increasing Fast Fourier Transform (FFT) and Discrete Cosine Transform (DCT) performance. The core can execute eight 16x16 multiply and accumulate instructions per cycle, twice as many as the current C64x DSP core. Since the new C64x+ instruction set is a superset of the C64x instructions, software for the new device is 100 percent object code compatible with code for existing C64x DSPs, permitting customers to leverage their software investment and get started with the new C6455 DSP right away. Benchmarked independently by Berkeley Design Technology, Inc. (BDTI), an independent analyst firm, TI’s C64x+ DSP Core at 1 GHz received a BDTIsimMark2000™ of 10980, the highest score BDTI has published for a DSP to date. (The BDTIsimMark2000™ provides a summary measure of DSP speed. For more info and scores, see www.BDTI.com. Scores © 2005 BDTI.)

"TI´s heavy lifter C64x+ based enhanced engines can now talk to each other at high speed in multiprocessing configurations," said Max Baron, principal analyst at In-Stat. “The Serial RapidIO on the C6455 has the high bandwidth and protocols to enable increases in infrastructure and imaging system performance at lower cost through reduction of chip count and board area.”

“As the telecom, imaging, networking and video industries continue to develop new services, the C6455 DSP’s programming flexibility allows developers to keep pace with changes in standards and to quickly implement multiple voice and video codecs in their system designs,” said Thomas Brooks, DSP platform marketing manager, TI.


Comprehensive Support Speeds Development

TI’s Code Composer Studio™ integrated development environment (IDE), the industry’s most comprehensive and intuitive IDE for DSPs, includes the industry’s most advanced optimizing C compiler and code-tuning development tools. The industry’s most robust network of DSP third parties helps simplify development and speed time-to-market with algorithms for applications such as videoconferencing, voice and video gateways, media servers and advanced Computer Telephony Integration (CTI) messaging. Because the C6455 DSP is 100 percent code-compatible with earlier C64x DSPs, customers can start development immediately leveraging the C compiler, assembler, linker and simulator available today.

High-Speed Amplifier Well-Suited for Infrastructure and High-End Imaging

TI also offers the THS4509, the lowest noise, lowest distortion fully-differential amplifier for driving high-speed analog-to-digital converters (ADC) such as the ADS5500 14-bit, 125-MSPS ADC. TI’s high-performance analog and DSP products provide a state-of-the-art signal chain for wideband applications. For more information on THS4509 please visit www.ti.com/ths4509.


Availability, Packaging and Pricing

Based on TI’s advanced 90-nanometer CMOS (complementary metal-oxide-silicon) technology, the TMS320C6455 DSP will be offered by TI in 1 GHz, 850 MHz and 720 MHz versions. Order entry for pre-production units will open on June 27, 2005 with initial shipments in third quarter 2005. Volume production is scheduled for the second quarter of 2006. The device will be available in a 697-pin 24 x 24 mm BGA (ball grid array) package. Planned pricing is $259 per 1 GHz unit, $219 per 850 MHz unit, and $179 per 720 MHz unit in quantities of 10K units.