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TI Introduces Industry's Smallest LVPECL/LVDS Oscillator Buffers

Devices Combine Low Jitter and Power with High Speed

Mar 3, 2005

DALLAS (March 3, 2005) - Texas Instruments Incorporated (TI) (NYSE: TXN) today introduced eight new high gain output oscillator buffers. Measuring just 2 x 2 x 0.55 mm, the new oscillator products enable designers to save space while also minimizing jitter and power consumption. The devices provide differential signal output in low-voltage differential signaling (LVDS) or low-voltage pseudo emitter-coupled logic (LVPECL) and clock signal amplification for telecommunications switching equipment. (See www.ti.com/sc05057.)


The SN65LVDS16/17/18/19 and SN65LVP16/17/18/19 are high-frequency oscillator gain stage buffers supporting LVDS and LVPECL on the high gain outputs in 3.3-V or 2.5-V systems. The devices afford oscillator designers their choice of rise times: 2 Gbps (LVDS/LVP16 and LVDS/LVP17) and 1 Gbps (LVDS/LVP18 and LVDS/LVP 19). In addition, the family provides the option of both single-ended input on the LVDS/LVP16 and LVDS/LVP18 and fully differential inputs on the LVDS/LVP17 and LVDS/LVP19. The LVDS/LVP16 and LVDS/LVP18 provide three gain control options from 300 mV to 860 mV, allowing the designer to optimize the buffer based on system needs.
The new devices offer 3.3-V and 2.5-V operation, enabling designers to migrate seamlessly to 2.5-V supply as system needs dictate. Each device offers power savings when compared to the nearest competition, with power reductions ranging from 15 percent to 66 percent. For example, the LVP18/19 each uses only 50 mW, about one-third the power consumption of comparable devices.
The new devices join other TI oscillator products such as the CDCM1802/04. These mixed-output low-voltage PECL and low-voltage transistor-to-transistor (LVTTL) devices provide timing module and voltage-controlled crystal oscillator designers integrated low-voltage PECL and LVTTL outputs in a 3 x 3 mm and 4 x 4 mm package, respectively. This is especially useful for designers who need a LVTTL feedback in their PLL module design. The buffers also include multiple divider options, which are chosen through external select pins. The devices are well-suited for communications applications. For more information about TI´s complete portfolio of DSP and analog products that enable engineers to speed design of their wired and wireless communications equipment, please see the Communications Solutions Guide at www.ti.com/sc05057b.

Key Features

  • Low-Voltage PECL input and Low-Voltage PECL or LVDS outputs 
  • Clock rates to 2 GHz (LVDS/LVP16 and LVDS/LVP17)
    • 140-ps output transition times
    • 0.11-ps typical intrinsic phase jitter
    • less than 630-ps propagation delay times
  • Clock Rates to 1 GHz (LVDS/LVP18 and LVDS/LVP19)
    • 250-ps output transition times 
    • 0.12-ps typical intrinsic phase jitter
    • less than 630-ps propagation delay times
  • 2.5-V or 3.3-V supply operation

Availability, Pricing and Support

The SN65LVDS16/17/18/19 and SN65LVP16/17/18/19 are available in volume from TI and its authorized distributors, packaged in an eight-pin, 2 x 2 x 0.55 mm Lead (Pb)-Free small-outline no-lead package. Suggested resale pricing in 1,000-piece quantities is $2.55 each for the LVDS16/17/18/19 and $1.95 for the LVP16/17/18/19.


Samples are available for 24-hour delivery.