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Texas Instruments Discloses Techniques for Highly Integrated, System-on-a-Chip Products at ISSCC 2005

Technical Papers Demonstrate Mixed-Signal Capability of Advanced 90nm Process

Feb 7, 2005

SAN FRANCISCO - February 7, 2005 - At the prestigious 39th annual IEEE International Solid-State Circuits Conference (ISSCC) this week, Texas Instruments Incorporated (TI) (NYSE: TXN) is presenting a total of 16 papers and participating on two panel sessions, with the majority of the presentations focused on implementations of TI's 90-nanometer (nm) chip manufacturing process. At the conference TI is demonstrating how higher levels of analog and digital integration at 90-nm is driving higher performance, lower power consumption, and lower cost in wireless, broadband and digital consumer markets.
TI was among the first semiconductor companies to deliver working 90-nm products when it shipped its first 90-nm device in January 2003. Today, the company has delivered over six million devices built on the process and has over 20 different products in various stages of production.

Enabling SoC Integration

With the ability to pack over 400 million transistors on a single chip, TI´s 90nm process drives cost-effective, system-on-a-chip (SoC) solutions with the highest levels of performance and power savings. Its advanced integration capabilities support a wide range of analog and RF components, including TI´s unique, breakthrough Digital Radio ProcessorTM, or DRPTM architecture that simplifies radio frequency (RF) processing and dramatically cuts the cost and power consumption of the wireless transmit and receive functions. This approach extends battery life of wireless devices and frees board space for enhancing functionality of advanced multimedia devices. DRP also provides potential for modular radio configurations that can be integrated into products for seamless access to a range of network connections. 

TI's 90-nm process uses a collection of transistors that are "tuned" for different on-chip functions to meet a variety of performance, density and power consumption requirements. This is accomplished through adjustments to the transistors' gate length, threshold voltage, gate oxide thickness or bias conditions. Transistors with the highest performance can be used for critical functions such as signal processing, while transistors with lower power consumption can be used for supporting functions with lower active performance requirements. TI's approach is leveraged across several optimized 90nm process flows that address a variety of end products and application requirements.

Comprehensive List of Papers

Following is the list of the 90nm papers being presented by Texas Instruments at ISSCC 2005: 

  • 90-nm Low-Leakage SoC Design Techniques for Wireless Applications (Session 7.6) 
  • An Enhanced 90-nm High Performance Technology with Strong Performance Improvements from Stress and Mobility Increase through Simple Process Changes (Session SE4) 
  • A Low-Power Multi Bit Delta Sigma Modulator in 90-nm Digital CMOS without DEM (Session 9.2) 
  • A 66dB-DR 1.2V, 1.2mW Single-Amplifier Double-Sampling 2nd Order Delta Sigma ADC for WCDMA in 90-nm CMOS (Session 9.3) 
  • A 3.3mW 12MS/s 10b Pipelined ADC in 90-nm Digital CMOS (Session 15.2) 
  • A 90-nm CMOS Single-Chip GPS Receive with 5dBm Out-of-Band IIP3 2dB NF (Session 17.1) 
  • All Digital PLL and GSM/EDGE Transmitter in 90-nm CMOS (Session 17.5) 
  • A Low-Phase-Noise 0.004ppm/Step DCXO with Guaranteed Monotonicity in 90-nm CMOS (Session 22.5) 
  • A 4th Order 86dB CT Delta Sigma ADC with Two Amplifiers in 90-nm CMOS (Session 27.3) 
  • A Low-Noise, Low Voltage CT Delta Sigma Modulator with Digital Compensation of Excess Loop Delay (Session 27.4) 
  • I/Q Mismatch Compensation in a 90nm Low-IF CMOS Receiver (Session 29.7)

In addition to the strong number of TI´s papers focused on 90-nm process technology developments, company representatives are sharing their expertise through additional participation on panels and in papers that address integration advancements and viewpoints on issues or trends. These speaking engagements include:

  • Panel: What Papers Will and Will Not be at ISSCC 2010 (E2) 
  • Panel: RF MEMS: Fact or Stiction (E3) 
  • Transmit Architecture with 4-Tap Feed Forward Equalization for 6.25/12.5Gbps Serial Backplane Communications (Session 3.4) 
  • A 100 dB DR CMOS Image Sensor Using a Lateral Overflow Integration Capacitor (Session 19.4) 
  • SER in SRAMs (Session SE5) 
  • A Multi-Standard DSL Central Office Modem SoC (24.5) 
  • Dynamically Power-Optimized Channel-Select Filter for Zero-IF GSM (Session 27.7)

For a complete ISSCC schedule, please go to