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TI and Xilinx Provide Easiest-to-Use Interface Solution Between High-Speed Data Converters and FPGAs

Companies Release Deserializer Reference Design for the TI ADS527x Data Converter Family and the Xilinx Virtex-II and Spartan-3 FPGAs

Nov 1, 2004

DALLAS (Nov. 1, 2004) - Texas Instruments Incorporated (TI) (NYSE: TXN) and Xilinx (NASDAQ: XLNX), the world's leading supplier of programmable logic solutions, today announced immediate availability of an FPGA-based deserializer reference design jointly developed by TI and Xilinx. This new reference design, which deserializes bit streams from TI's ADS527x analog-to-digital converter (ADC) family, and accompanying application note provide a quick and easy solution for designers to integrate a serial, high-speed LVDS receiver into the Xilinx Virtex-II series, Virtex-II Pro and Spartan-3 FPGAs.
Systems designers can now effectively leverage the serial-to-parallel processing capabilities and software programmability of FPGAs to accelerate operations for specialized, high-performance processing functions. The ability to achieve much higher levels of overall system performance is especially important for multi-channel applications such as ultrasound, instrumentation and wireless communications. Designers can obtain more detailed information on how best to interface Xilinx FPGAs to TI´s high-speed data converters for their specific applications by going to www.ti.com/ADS527x. LVDS Reference Design files can also be downloaded directly from Xilinx at: www.xilinx.com/bvdocs/appnotes/xapp774.pdf

High Performance LVDS Interface

The deserializer reference design accepts up to eight channels simultaneously and provides automatic de-skew and clock alignment functions. Each ADC output is serialized and transmitted through a separate LVDS serial pair. An independent frame clock and serial data clock are provided to allow for easy de-serialization. The Xilinx reference design provides the necessary timing to accept these extremely fast input signals and translate them into commonly used parallel output busses.

The serial LVDS interface format provides several distinct advantages to the system manufacturer. Lower pin count, both on the ADC and the FPGA, means less routing lines and lower cost boards. The LVDS interface itself is a differential current mode interface that provides both immunity to external noise and extremely low crosstalk injection of noise into the printed circuit board. These advantages translate to lower cost and higher system reliability.

About TI´s ADS527x Data Converters

The ADS527x family of eight-channel ADCs includes 40, 50, 65 and 70 MSPS (mega samples per second) versions in 12-bit resolution, and 40, 50 and 65 MSPS versions in 10-bit resolution. All products in this family are pin compatible, providing a simple upgrade path in both sample rate and resolution.

The ADS527x family features exceptional signal-to-noise ratio of 70.5dB (60.5dB for the 10-bit family) at 10MHZ input frequency and only 123mW of power per channel at 65 MSPS (138mW/channel at 70 MSPS) - the lowest power of any competitive product. The devices allow high system density for multi-channel applications. (See www.ti.com/sc04020 for product information).

About Xilinx FPGAs

Xilinx Virtex-II series Platform FPGAs deliver the highest performance and highest density of any programmable logic solution available today. With densities ranging from 40,000 to eight million-system gates, Virtex-II and Virtex-II Pro Platform FPGAs have been broadly adopted in sophisticated, high-performance applications historically dominated by application-specific integrated circuits (ASICs).

Spartan-3 is the only low-cost FPGA that provides up to 344 differential I/O pairs for LVDS interfacing. Combined with the break-through price points offered by these devices, companies can now implement one of the lowest cost LVDS deserializer designs with Spartan-3 FPGAs.