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NATIONAL SEMICONDUCTOR LEADS INDUSTRY/UNIVERSITY CONSORTIUM TO IMPROVE CHIP YIELDS, REDUCE COSTS

Three-year, $18.6 million Joint Program Launched; 40 Percent Improvement Already Seen in Key Wafer Fabrication Process Step

Oct 8, 1998

Santa Clara, CA, October 8, 1998 -- The US government?s National Institute of Standards and Technology (NIST) has selected National SemiconductorÒ as the lead company of a broad industry/university consortium to develop technologies that significantly improve chip yields and reduce costs.

The Advanced Technology Program for the Intelligent Control of the Semiconductor Patterning Process is designed to restore the historical 25 to 30 percent annual reduction in the cost per function of semiconductors. Participants in the three-year, $18.6 million program -- to improve efficiency and interaction among measurement tools, production equipment and operating software -- include three semiconductor equipment companies, four major universities and several key subcontractors.

"The program to improve chip yields is designed to solve a crucial, growing issue with manufacturers of advanced chips," said Gobi Padmanabhan, National?s senior vice president for technology research and development. "As the critical dimensions or geometries of circuit elements shrink to 0.18 microns and smaller, they too often are tinier than what can be consistently measured process step by process step." This lack of uniformity directly affects yields and costs.

Improving Chip Yields

Improving uniformity through this NIST program will enable semiconductor manufacturers to produce more chips with consistently higher yields. It also will allow National, for example, to further integrate more complex functions onto silicon to develop complete system-on-a-chip solutions, Padmanabhan says. Importantly, the results of NIST?s program will be available to the entire US semiconductor industry, benefiting everyone.

Central to improving uniformity is the semiconductor patterning process. This is the interaction of lithography equipment to print the circuit layers as they are integrated to form chips and the etch steps that solidify the critical dimensions for each layer, controlled by operational software. Improved uniformity of the critical dimensions (CDs or geometries) of circuit lines created during the manufacturing process will produce higher yields of fully functional chips.

On-line feed-forward control (FFC) is essential in that process. By measuring the CDs after a photolithography step, process managers can make changes in the next etch step to improve yields. National already has seen a 40 percent improvement in variance of CDs using FFC during the crucial process step involving the cornerstone polysilicon layer in its advanced CMOS wafer fabrication line in South Portland, Maine.

NIST is sponsoring the research on improved chips because the semiconductor industry is viewed as an enabling industry to the entire US economy. Semiconductors are used in virtually all industrial, automotive, telecommunications, computing, military, and many consumer products, NIST says. For the past 20 years, the semiconductor industry has been growing at an annual rate of 19 percent, and is considered a key driver of US economic growth. The ability to continue this rate of improvements and lower costs depends on the printing of ever-smaller features on silicon wafers. Patterning is the single most critical and capital-intensive part of the wafer fabrication process, and the one needing the most co-operative attention, the institute concludes.

Expected benefits of the joint program include:

  • Increased yields from improved patterning (lithography and etch-step) process that prints the circuit elements onto the chips in production,
  • Improved production efficiency due to reduced set-up time and reliance on consistent test wafers,
  • Increased productivity by replacing slow off-line measurement with responsive in-line and in-situ metrology,
  • Extension of the useful life of existing semiconductor production equipment systems.

NIST also chose National as the lead company in a separate three-year, $5.7 million program to develop new materials that make it more efficient to bond so-called flip-chip packages to substrates on printed circuit boards.

The joint-venture partners are FSI International (Allen, Texas), KLA-Tencor (San Jose, Calif.), Lam Research Corp. (Fremont, Calif.), Stanford University (Stanford, Calif.) and the University of Michigan (Ann Arbor, Mich.). Key subcontractors include the University of California at Berkeley, the University of California at Irvine, Jack Mott (Idaho Falls, Idaho), Spain, Inc. (Portola Valley, Calif.), Integrated Systems, Inc. (Sunnyvale, Calif.) and IBM Global Production Solutions (Boca Raton, Fla.). Cost of the program is split approximately 50% between NIST and the participants.

About National

National Semiconductor provides system-on-a-chip solutions for the information age. Combining real-world analog and state-of the-art digital technology, the company's chips lead many sectors of the personal computer, communications, and consumer markets. With headquarters in Santa Clara, California, National has annual sales of approximately $2.5 billion and 12,000 employees worldwide. Additional company and product information is available on the World Wide Web at www.national.com.