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Cyrix Unveils Jalapeno Architecture

Next generation processor delivers cutting-edge performance, advances integrated platform strategy

Oct 13, 1998

October 13, 1998 -- Cyrix® Corporation, a subsidiary of National Semiconductor Corporation? (NYSE:NSM), today revealed the architecture for its next generation processor core, code-named Jalapeno, at Microprocessor Forum '98. Jalapeno will deliver unmatched performance and value for the mainstream PC market while continuing the innovative integration pioneered by Cyrix. The first completely new architecture from Cyrix since the original 6x86 processor, Jalapeno will run at 600+ MHz clock speeds, overcome memory bottlenecks and deliver industry-leading 3D graphics capabilities. Jalapeno is designed from the ground up to take advantage of state-of-the-art technology to minimize die-size for low-cost manufacturing.

The Jalapeno design includes an 11-stage deep-pipeline, a completely new floating point unit, a 3D graphics engine and numerous memory enhancements, all of which combine to deliver outstanding improvements in overall system performance.

The design philosophy behind Jalapeno reflects National Semiconductor's corporate vision -- to make low-cost, high-performance Windows?-compatible computing power available for mainstream business users and consumers. This latest core technology will be the soul of the M3, Cyrix's next generation processor, expected to debut in the fourth quarter of 1999 in the 600 - 800MHz speed range.

"We designed Jalapeno to deliver the highest performance engine for the mainstream PC market," said Stan Swearingen, vice president of marketing for Cyrix. "We found that the most significant bottlenecks in system performance result from memory latency. Since our goal was to optimize overall system performance, we focused our attention on minimizing memory latency and maximizing bandwidth by implementing an innovative on-chip caching scheme and memory controller. The high level of integration minimizes die size, which means we can manufacture at low cost and provide the best value in a high-performance processor."

Design Objectives
Jalapeno was designed with four main objectives in mind -

  • Operate at high clock speeds
  • Reduce memory latency and bottlenecks
  • Improve floating-point and 3D graphics performance
  • Minimize die size to deliver an integrated, low-cost solution.

Jalapeno's deep pipeline and on-chip L2 cache are designed to overcome bottlenecks typically associated with high-speed processors. By using an 11-stage pipeline, the design provides for scalability to beyond one gigahertz clock speeds. The 256K on-chip L2 cache is 8-way associative, 8-way interleaved and fully pipelined to operate at the core frequency. This will enable performance comparable to a typical 512K on-chip cache. The graphics subsystem can use the L2 cache for texture caching and as a composite buffer for multi-pass graphics features. An on-chip memory controller, another feature of the design, provides a dramatic improvement in memory bandwidth, allowing for a 3.2 GB per second transfer rate.

Jalapeno's new floating point unit has dual independent FPU/MMX units and includes both a fully pipelined, independent x87 adder and x87 multiplier. The Jalapeno design facilitates close integration between the core and the advanced 3D graphics engine, which will be one of the first graphics subsystems to utilize a dual-issue FPU. The dual FPUs support execution of both MMX and 3DNow! instructions. 3DNow! was jointly-developed by Cyrix, AMD and Centaur Technology.

Jalapeno also incorporates consumer-quality DVD playback capabilities based on technology developed by National's Mediamatics subsidiary.

Jalapeno will be produced using National's state-of-the-art 0.18 micron process technology, which is currently running in the company's development labs at the South Portland, Maine fabrication facility. The design and process technology have been closely matched to provide the best combination of high performance and small die size -- expected to be approximately 110 - 120 sq. mm.

"Our ramp up time to the 0.18 micron process technology has been nothing short of phenomenal, " said Kevin McDonough, co-general manager of Cyrix and senior vice president of National Semiconductor. "The new Jalapeno core is designed to deliver cutting-edge performance in an integrated environment, and we've optimized it for cost-efficient manufacturing on state-of-the-art process technology."

Cyrix Corporation

Cyrix, a wholly owned subsidiary of National Semiconductor, is a leading supplier of innovative processor-based solutions that set new standards for the personal computer market. Cyrix delivers compelling value and quality to its customers, the manufacturers of personal computer products, by combining industry-leading design with world-class manufacturing. Cyrix's MediaGX? processor pioneered the sub-$1,000 PC market in 1997 and continues to lead the market to higher performance at lower prices.

National Semiconductor Corporation

National Semiconductor provides system-on-a-chip solutions for the information age. Combining real-world analog and state-of the-art digital technology, the company's chips lead many sectors of the personal computer, communications, and consumer markets. With headquarters in Santa Clara, California, National has annual sales of approximately $2.5 billion and 12,000 employees worldwide. Additional company and product information is available on the World Wide Web at