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New multicore system-on-a-chip architecture from Texas Instruments to deliver 5X performance and simplified design for communications infrastructure equipment

PRNewswire
Feb 15, 2010

BARCELONA, Spain, Feb. 15 /PRNewswire/ -- MOBILE WORLD CONGRESS -- Texas Instruments Incorporated (TI) (NYSE: TXN) today unveiled a new System-on-a-Chip (SoC) architecture based on its multicore digital signal processors (DSPs) that integrates fixed and floating point capabilities in the industry's highest performing CPU.  Running at up to 1.2GHz and providing an engine with up to 256 GMACS and 128 GFLOPS, TI's new multicore SoCs deliver over five times the performance of existing solutions in the market and offer vendors a common platform to accelerate the development of infrastructure products such as wireless base stations, media gateways and video infrastructure equipment.  

"If TI delivers on its performance projections, it will clearly be raising the bar on performance for mainstream DSPs," said the respected technology analysis firm BDTI in its InsideDSP newsletter.  "TI's decision to focus more on providing a multicore programming development methodology and environment could give TI an ease-of-use edge over other DSP processor vendors."

Key features and benefits:

  • Multiple high-performance DSPs operating at up to 1.2GHz in an innovative SoC architecture;
  • Integrated fixed and floating point processing within each DSP core combining ease-of-use with unprecedented signal processing performance;
  • Robust suite of tools, application-specific software libraries and platform software enabling faster development cycles and more effective debug and analysis;
  • Five times the DMA capability and twice the memory per core of other SoCs ensuring robust application performance for customers;
  • Product family to include range of devices starting with four-core device for wireless base stations and eight-core device for media gateway and networking applications;
  • Direct communication between cores and memory access with TI's Multicore Navigator freeing peripheral access and unleashing multicore performance;
  • A 2 terabit per second on-chip switch fabric, TeraNet 2, providing high bandwidth and low latency interconnection of all of the SoC elements;
  • A Multicore Shared Memory Controller allowing faster on-chip and external memory access;
  • High-performance layer 1, layer 2 and network co-processors.

 

"Manufacturers of communications infrastructure equipment have very specific requirements for differentiating their products and innovating beyond a single portfolio.  It was clear to us that TI had the opportunity to introduce a new platform to customers with a 'smart design' approach that meets their needs for years to come," said Brian Glinsman, general manager of TI's communications infrastructure business. "With this new multicore architecture, we challenged ourselves to exceed Moore's Law by bucking the trend of simply linearly increasing the amount of cores on each platform; instead, we increased overall performance with significant enhancements to the DSP, a new breed of coprocessors, and reduced power consumption."

Availability

Products from the new multicore portfolio will begin sampling in the second half of 2010.

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SOURCE Texas Instruments Incorporated