News Room : clocks and timers

Texas Instruments expands its precision timing portfolio with industry's most highly integrated clock generator family

NewsCenter — Thu, 23 Apr 2009 08:00:00 GMT

Compact clocking solutions save up to 50 percent board space

DALLAS (April 23, 2009) - Texas Instruments Incorporated (TI) (NYSE:TXN) today introduced three new precision clock generators that have a crystal input, replacing up to four discrete high-frequency crystal oscillators with a single device. These devices provide a more cost-efficient solution that saves up to 50 percent more board space than competing solutions today. The CDCM61004 family improves system performance by achieving integrated RMS jitter of 500 fs, well suited for data communications equipment. For product details and to order samples see: www.ti.com/cdcm61004-pr.

The CDCM61004 family eases board design by providing a fully integrated voltage-controlled oscillator (VCO) support for a wide output frequency range from 43.75 MHz to 683 MHz, allowing one device to cover multiple standards or multiple designs. The clock generators operate at less than 500 mW to enable high-density designs, offering up to 30 percent power savings.

Key Features

Input reference including the commonly used crystal frequencies such as 24.8832 MHz, 25 MHz, and 26.5625 MHz
On-chip VCO operates in frequency range 1.75 GHz to 2.05 GHz, supporting output from 43.75 MHz to 683 MHz
Input crystal bypass mode allows direct tuning on the reference
Output selectable between LVPECL, LVDS or 2-LVCMOS

Key Benefits

Pin-compatible family allows the same hardware strapping
High integration and flexible I/O minimizes the number of components
Reduces board space and provides a cost-efficient solution
Low jitter improves overall system bit error rate performance
Low power enables high-density designs

Availability and pricing

The CDCM61004 family is available now in volume production in a QFN-32 package. The CDCM61004 has four LVPECL/LVDS or eight LVCMOS outputs and is priced at $8.15. The CDCM61002 has two LVPECL/LVDS or four LVCMOS outputs and is priced at $6.25. The CDCM61001 has one LVPECL/LVDS or two LVCMOS outputs and is priced at $5.25. All pricing is in quantities of 100 units.

Find out more about TI's clock portfolio by visiting the links below:

Order CDCM6100x evaluation modules and samples: www.ti.com/cdcm61004-pr
Watch CDCM6100x informational video: www.ti.com/cdcm61004video
See TI's complete clocks and timing portfolio: http://clocks.ti.com
Get questions answered on TI's E2E online community: http://community.ti.com .

TI announces industry's first full production release of DDR3 register

NewsCenter — Tue, 15 Apr 2008 08:00:00 GMT

Device delivers high stability for memory modules

DALLAS (April 15, 2008) - Texas Instruments (TI) (NYSE: TXN) today announced the industry's first full production release of a phase locked loop (PLL) integrated DDR3 register for registered dual in-line memory modules (RDIMMs). This device enables system stability through constant clock and output delay over voltage and temperature variation. The single-chip quad rank support saves overall board space and reduces power consumption in servers, work stations and storage equipment. (See www.ti.com/sn74ssqe32882-pr.)

The SN74SSQE32882 28-bit to 56-bit registered buffer operates at 1.5 V VDD and supports parity features to ensure reliability. It provides flexibility by supporting high data rates of 800 Mbps to 1,333 Mbps and can support up to 72 DRAMs on one module.

Other key features include the following:

CKE power down
Control mode register
Output driver strength control
Operating frequency: 300 to 670 MHz

The SN74SSQE32882 exceeds the requirements for stability over temperature and voltage defined by the Joint Electron Device Engineering Council. This ensures reliability in high-performance server systems.
"TI is pleased to offer the first qualified and fully compatible DDR3 register to the market," said Nick Hassan, general manager of TI's Interface and Clock products group. "By working with leading industry partners, TI has designed the SN74SSQE32882 to exceed the stringent performance and stability requirements of DDR3 systems."

DDR solutions ease design

TI's DDR3 register adds to a complete portfolio of leading DDR2 registers and PLL devices such as the CDCUA877 and SN74SSTUB32866. In addition, the TPS51116 and TPS51100 DC/DC controllers significantly reduce the number of external components that support all the power management requirements for DDR systems.

Availability

The SN74SSQE32882 is available now in a 176-ball MicroStar^TM BGA package. Suggested resale pricing in 1,000-unit quantities is $5.90.

TI Introduces Industry's Most Flexible 3.3-V, 2.5-V and 1.8-V Clock Generator Family

NewsCenter — Tue, 10 Jul 2007 08:00:00 GMT

Low-Jitter, One- to Four-PLL Devices Ease Design for Consumer Applications

DALLAS (July 10, 2007) - Texas Instruments (TI) (NYSE: TXN) today introduced a family of highly-programmable, one to four phase-lock loop (PLL) clock generator devices with the ability to generate up to nine output clock sources from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz. These features provide a number of system benefits such as reduced power consumption, shorter lead time and the flexibility to easily upgrade the clock without redesigning the system. These benefits ultimately reduce cost for a broad range of consumer applications such as IP set-top boxes or phones, digital media systems such as digital televisions, streaming media and printers, navigation systems and portable devices. (See www.ti.com/CDCE949-pr.)

The new CDCE9xx and CDCEL9xx family of clock generators ranges from one to four PLLs with very low jitter at 60 picoseconds typical. The CDCE9xx devices provide either 2.5-V or 3.3-V outputs, and the CDCEL9xx provide 1.8-V outputs, enabling the low-power capability needed for portable devices. Each PLL supports spread-spectrum clocking (SSC) to reduce electro-magnetic interference (EMI) to enable compliance with EMC regulations.
The family provides a variety of programmability options including the ability to program and customize the devices in-system through I2C and EEPROM. By offering footprint compatibility across the family, designers can adapt the system design easily without changing hardware, which reduces cost and enables the designer to simply increase or decrease the number of clock outputs. The new family of devices further simplifies system design by replacing a number of components in the system including crystals, oscillators, buffers and PLLs.
The new clock devices are optimized to work with TI's DaVinci^TM-based processors by generating any audio, video, processor or interface clock to drive the digital processor, audio digital-to-analog converter or codec and Ethernet or USB controller. The on-chip voltage-controlled crystal oscillator (VCXO) allows frequency synchronization of different data streams.
TI provides a wide selection of timing support devices, both PLL-based and non-PLL-based, to support consumer, communications and memory applications. Information on the complete line of clock products from TI is in the Clocks and Timers Selection Guide, available at www.ti.com/clocks.
New Clock Generator Family

Availability

The CDCE949 is available now in 24-pin TSSOP package. The remaining devices in the family will be available throughout 2007 in 20-pin, 16-pin and 14-pin TSSOP packages. In addition, evaluation modules (EVMs) to evaluate the performance of the family are available.

Texas Instruments Introduces True Femto-Second Performance Clock Generator for Networking Designs

NewsCenter — Wed, 06 Jun 2007 09:00:00 GMT

High-Performance, Fully-Integrated Clock Reduces Design Time and Cost

DALLAS (June 6, 2007) - Texas Instruments (TI) (NYSE: TXN) today introduced a low-phase noise clock generator that provides best-in-class jitter performance at 380 femtoseconds (fs) (rms at 10 kHz to 20 MHz). The device incorporates crystal oscillator (XO) circuitry with a fully-integrated frequency synthesizer supporting a wide output frequency range from 10.9 MHz up to 766.7 MHz and from 875.2 MHz up to 1175 MHz, easing design for customers designing Ethernet, fibre channel, PCI Express and Serial ATA products. (See www.ti.com/CDCE421-pr.)

The CDCE421 is available in either its die form to fit in a 5-mm x 7-mm XO package or a 24-pin quad flat no-lead (QFN) package, giving customers flexibility to fit their designs. The new clock device is the first to integrate both on-chip EEPROM and XO circuitry for increased programmability, further simplifying the design by allowing the customer to implement a single device for various frequencies.

All device settings are programmable through a TI proprietary simple serial interface for programming after manufacturing. The device operates in a single 3.3 V supply environment and is characterized for operation in the industrial temperature range from -40C to +85C. Other key features include the following:

Support for crystal or LVCMOS frequencies between 27.35 MHz and 38.33 MHz
Low-voltage differential signaling (LVDS) Output, 100-ohm differential off-chip termination, 10.9-MHz to 400-MHz frequency range
Differential low-voltage positive emitter-coupled logic (LVPECL) Output, 10.9-MHz to 1.175-GHz Frequency Range
Fully-integrated programmable loop filter from 50 kHz to 400 kHz
Typical power consumption 240 mW in LVDS mode and 300 mW in LVPECL mode
Chip-enable control pin
Electrostatic discharge protection exceeds 2-kV human-body model
Excellent power supply noise rejection

TI provides a wide selection of timing support devices, both PLL-based and non-PLL-based, to support consumer, communications and memory applications. Information on the complete line of clock products from TI is in the Clocks and Timers Selection Guide, available at www.ti.com/clocks.

Pricing and Availability

The CDCE421 is available now in either a die form or packaged in a 24-pin QFN package and is priced at $7.00 in 1,000-piece quantities.

TI Introduces Industry's First DDR3 Register for Memory Modules

NewsCenter — Tue, 07 Nov 2006 08:00:00 GMT

Fully-Integrated DDR3 Register Simplifies Design, Saves Power and Board Space

DALLAS (Nov. 7, 2006) -- Texas Instruments (TI) (NYSE: TXN) today introduced the industry's first fully-integrated register and phase-locked loop (PLL) for DDR3 registered dual in-line memory modules (RDIMMs). This single-chip device supports high data rates of 800 mega transfers per second (MT/s) to 1,066 MT/s. The device also reduces power consumption and board space to simplify the design of next-generation DDR3 memory modules for servers and workstations. (See www.ti.com/sc06208.)

Manufactured in TI's 130-nm process technology, the SN74SSTE32882 also integrates a high-performance, low-skew buffer with the register and low-jitter PLL. Integration of the PLL eliminates the need to tune the memory module, greatly simplifying design and board layout to accelerate server and RDIMM manufacturers' market entry. Customers can also enjoy improved performance and reliability with the integration of these features.
The SN74SSTE32882 28-bit 1:2 configurable registered buffer is designed for 1.5-V VDD operation for high speed and low power consumption. One device per DIMM is required to drive up to 36 SDRAM loads. The edge-controlled circuit outputs meet SSTL_15 specifications and are optimized for terminated DIMM loads. To provide maximum flexibility and support industry-standard DIMM configurations, the clock and control outputs can be programmed with differing drive strengths.
The SN74SSTE32882 fully supports parity features as defined by Joint Electron Device Engineering Council (JEDEC). This parity function improves reliability of server systems. The SN74SSTE32882 also supports spread spectrum clocking (SSC) to reduce EMI.
"The SN74SSTE32882 is the first device on the market enabling the future of cost- and power-efficient registered DIMMs for next generation servers and high-end PCs," said Kent Novak, general manager of TI's high-speed communications group. "This device is a result of TI's analog technology leadership and cooperation with industry-leading chipset vendors, server OEMs and DIMM manufacturers."
Information on available DDR3 RDIMMs and the complete line of clock products from TI is in the Clocks and Timers Selection Guide, available at www.ti.com/clocks.

Availability

The SN74SSTE32882 is packaged in a 176-pin BGA with 0.65 mm ball pitch in an 11 x 20 grid. It is sampling today and will be in full production in 3Q2007.

TI Introduces Hot-Programmable, Highly Stable Clock Multiplier for Consumer Applications

NewsCenter — Thu, 08 Dec 2005 08:00:00 GMT

In-System Spread Spectrum Clocking Eases Audio and Video Designs

DALLAS (Dec. 8, 2005) - Texas Instruments (TI) (NYSE: TXN) today announced a programmable clock multiplier with low jitter of 60 psec and in-system spread spectrum adjustment that improves performance, simplifies development and saves cost in consumer applications. Designers can hot program the device's three phase locked loop (PLL) components in-circuit to generate six output clocks from a single source for any frequency up to 167 MHz, which speeds development of equipment such as digital set top boxes, digital televisions (DTV), DVD players, audio/video (A/V) receivers and printers (see www.ti.com/sc05255). The device is well-suited for clocking high-performance processors, including DaVinci^TM products.

The CDCE906 provides advantages to help designers meet the performance requirements of consumer applications. For example, the high-resolution PLL dividers of the CDCE906 provide a very low-jitter clock from a single 27-MHz crystal clock and feature zero-PPM output clock error for most A/V frequencies and applications. This enables customers to achieve precise video and audio clock performance, including requirements for high-performance audio data converters like the PCM1850 stereo audio analog-to-digital converter for DTVs.
Another key performance enhancement is provided by the device's hot-programmable spread spectrum clocking (SSC), which lowers system electromagnetic interference (EMI) and helps reduce the need for a metal shield to block EMI. Hot-programmability enables designers to adjust the level of SSC on the fly, so they can rapidly fine-tune to optimize the system for EMI compliance qualification and also reduce the need for board redesigns for different applications. Programmable output slew-rate control and selectable output voltages of 2.5 V and 3.3 V further reduce system EMI. System performance also benefits from the device's extremely low jitter of 60 psec.
Often, designers of A/V equipment must clock several devices such as a digital signal processor (DSP) or application-specific integrated circuit (ASIC) on their system board. The CDCE906 makes this process easier and faster and reduces system costs by providing multiple programmable outputs. It can accept a differential, LVCMOS or crystal input and generate six clocks from a single clock source. Using on-chip EEPROM technology, designers can easily program and save the device's register settings in non-volatile memory so that no re-programming is required at power-up. In addition, designers can use the 2-wire SMBus interface to dynamically reprogram the outputs while the device is in the system.
The CDCE906 is the latest in TI's extensive portfolio of high-performance analog and DSP products for audio applications, including audio data converters, the Aureus^TM family of audio DSPs, PurePath Digital^TM audio amplifiers and Class-D audio amplifiers. TI provides the silicon, software, systems expertise and support for the entire audio signal chain, enabling customers to get to market quickly. For more information see www.ti.com/audio. In addition, TI offers high-performance power management products for consumer applications (power.ti.com).
Information on the complete line of clock solutions from TI is in the Clocks and Timers Selection Guide, available at www.ti.com/clocks.

Availability and Pricing

The CDCE906 is sampling today and will be in full production in 1Q2006. Suggested resale pricing is $2.60 each in 1,000-unit quantities. A development kit and programming kit will be available to simplify PLL design and programming. The device is 3.3 V supplied, operates in the commercial temperature range from 0ºC to 70ºC and is packed in a 20-pin thin shrink small outline package (TSSOP) package.

TI Announces Programmable, Flexible Clock Multiplier that Delivers 3x Better Jitter Performance

NewsCenter — Thu, 20 Oct 2005 00:15:00 GMT

Flexible Output Options Minimize Electromagnetic Interference

DALLAS (October 20, 2005) - Texas Instruments (TI) (NYSE: TXN) today announced a clock multiplier that integrates three on-chip phase locked loop (PLL) components to provide industry-leading flexibility and performance, including cutting period jitter by up to 70 percent compared to existing solutions and minimizing electromagnetic interference (EMI). Each of the device's six outputs can be programmed in-circuit or during operation for any clock frequency up to 300 MHz. This flexibility eases the design process, saves system cost and maximizes designers' ability to meet emerging standards in high-performance communications applications such as wireless base stations and telecommunications or data communications equipment. (See www.ti.com/sc05225.)

Developed in TI's radio frequency (RF) Silicon-Germanium process, the three PLLs of the CDCE706 can accept a crystal, LVCMOS or differential input and generate six clocks from a single clock source. Using on-chip EEPROM technology, designers can easily program and save the device's register settings in non-volatile memory so that no re-programming is required at power-up. Designers can also use the 2-wire SMBus interface to dynamically reprogram the outputs as needed while the device is in the system.
The CDCE706 enables fast time-to-market by easing the design process while providing very low period jitter of less than 60 psec. The user only needs to define the input and output frequencies or the divider setting, which automatically sets the PLL parameters. This in turn guarantees high loop stability and frees the user from manually setting the charge-pump current, filter components, phase margin or loop bandwidth. TI's RF process technology allows integration of such features while maintaining excellent PLL frequency isolation.
In addition, the new device features very flexible output settings such as enable, disable, low-state, signal inversion, slew-rate control of 0.6 ns to 3.3 ns, and variable output supply voltage of 2.3 V to 3.6 V. Along with programmable spread spectrum clocking (SSC), these features provide designers a powerful tool to optimize their designs for the lowest electromagnetic interference (EMI). Also, the device's high-resolution PLL dividers enable zero parts per million (PPM) output clock error for high frequency stability.

Available Today

The CDCE706 is sampling today and will be in full production in 1Q2006. Suggested resale pricing is $3.60 each in 1,000-unit quantities. A development kit and programming kit will be available to simplify PLL design and programming. The CDCE706 will also be available in factory-programmed versions for high-volume applications. The device is 3.3 V supplied, operates in the industrial temperature range of -40C to 85C and is packed in a 20-pin thin shrink small outline package (TSSOP) package.

TI's high-performance analog products and digital signal processors (DSP) optimized for wireless infrastructure applications comprise the industry's most complete signal chain solution for base station OEMs. In addition to the CDCE706, TI offers other high-performance analog products and DSPs, including the TMS320TCI6482 DSP. Nine of the top 10 base station OEMs use TI technology.
For information on TI's complete line of clock products for communications, consumer and memory applications, please see the Clocks and Timing Selection Guide at www.ti.com/clocks.

High-Performance RF Transmit Signal Chain Demonstration Kit from TI Speeds Wireless Infrastructure Designs

NewsCenter — Wed, 28 Sep 2005 09:00:00 GMT

DALLAS (Sept. 28, 2005) -- Texas Instruments Incorporated (TI) (NYSE: TXN) introduced today an easy-to-use radio frequency (RF) transmit signal chain demonstration kit that speeds time to market by cutting development time, risk and cost in wireless infrastructure (WI) applications. The demonstration kit provides a complete RF transmitter from digital baseband to analog RF, addressing the RF transmission needs of wireless base station or fixed wireless access equipment across all of today's wireless communication standards. (See www.ti.com/sc05200 for more information.)

The TSW3000 evaluation module (EVM) combines the DAC5687 16-bit, 500-MSPS interpolating digital-to-analog converter (DAC); the CDCM7005 low-phase-noise, low-jitter clock synthesizer and jitter cleaner; the TRF3702 low-noise direct quadrature modulator; and the TRF3750 high-performance, monolithic phase-locked loop (PLL) frequency synthesizer. Designers can use the kit as a working high-performance transmitter front-end chipset, as a tool to evaluate individual components' performance in an actual transmitter or as a means to verify system performance at the RF signal without incurring additional engineering costs.
The chipset minimizes noise and distortion, which are key performance issues in WI applications. When interfaced with the TRF3702 in-phase/quadrature (I/Q) modulator, the IQ compensation feature of the DAC5687 allows optimization of phase, gain and DC offset to maximize carrier suppression and sideband rejection, while maximizing power to the modulator. This, in turn, results in an excellent adjacent channel power ratio (ACPR) of 71 dB in a single-carrier WCDMA application at 30.72 MHz intermediate frequency (IF) with a RF local oscillator (LO) of 2.14 GHz. In a two-carrier WCDMA application, the chipset delivers an ACPR of 65 dB at 92.16 MHz IF with a RF LO of 2.14 GHz. In addition, the TSW3000 features I/Q modulation from 1.5 GHz to 2.5 GHz.
The TSW3000 provides a design solution that would otherwise cost WI base station manufacturers thousands of dollars in parts and labor and several months of design time. In addition, since all the components are manufactured and supported by TI, designers who use the kit as the basis for a reference design can enjoy one-stop shopping and take full advantage of TI's systems expertise and complete array of products, tools and technical support for high-speed designs.
The TSW3000 joins other TI tools and solutions for base station designers, including the GC5016 System Evaluation Kit (GC5016SEK) for evaluating TI's wideband quad digital down-converter/up-converter, and the TSW1100 data capture card and software for evaluating the company's WI-optimized high-speed analog-to-digital converters.
TI also offers a strong line of high performance, low power digital signal processors optimized for wireless infrastructure applications. TI is the only semiconductor provider to offer a complete signal chain solution, and nine of the top 10 3G base station OEMs use TI technology.

Availability

The TSW3000 is available today from TI. The price of $499 includes the EVM, User's Guide, software, termination resistors, datasheet for each component, power supply and parallel port cable.

TI Introduces High-Performance Clock Synthesizer and Jitter Cleaner

NewsCenter — Thu, 23 Jun 2005 08:00:00 GMT

High-Frequency Outputs with Lowest Phase Noise and Jitter Enable Clean Data Converter Clocking

DALLAS (June 23, 2005) -- Texas Instruments Incorporated (TI) (NYSE: TXN) introduced today a clock synthesizer and jitter cleaner that offers the lowest phase noise and jitter in its class. The device addresses customers' growing requirement for higher performance and increased design flexibility in applications such as 2.5G/3G wireless base stations, data communications, medical imaging, and test and measurement. (See www.ti.com/sc05137 for more information.)

The CDCM7005 provides precise, stable frequencies for signal-chain devices such as analog-to-digital converters (ADC), digital-to-analog converters (DAC), digital upconverters (DUC) and digital downconverters (DDC). It offers the industry's lowest phase noise of -219 dBc/Hz (PLL figure of merit), lowest phase jitter performance of 162 fs (LVPECL) and 232 fs (LVCMOS), and maximum output skew of 20 ps. This performance allows data converters such as ADCs to be undersampled at higher input frequencies while delivering the highest signal-to-noise ratio.
The CDCM7005 offers features that maximize design flexibility, including serial peripheral interface (SPI) logic for programming and individual support control. The device synchronizes a voltage-controlled crystal oscillator (VCXO) frequency up to 2.2 GHz (LVPECL) to one of two reference clocks to deliver high-frequency, clean clock outputs. The outputs can be divided by 1, 2, 3, 4, 6, 8 or 16 divide ratios and delivered at LVCMOS and LVPECL levels.
Other useful features include the device's bias voltage (VBB) pin, which allows it to supply the correct voltage to a single-ended VCXO, eliminating the need for external resistors and thereby simplifying the design. In addition, the CDCM7005 supports frequency hold-over mode and fast-frequency locking for failsafe and increased system redundancy.

Availability

The 3.3-V CDCM7005 is available today in industrial temperature range (-40C to 85C) from TI and its authorized distributors in either a 64-pin, 0.8-mm ball-grid array (BGA) or 48-pin, 0.5-mm quad flat no-lead (QFN) package. Suggested resale pricing in 1,000-piece quantities is $10.75. An evaluation module is also available.

TI's analog products and digital signal processors (DSP) optimized for wireless infrastructure applications comprise the industry's most complete signal chain solution for base station OEMs. In addition to the low-noise CDCM7005, TI offers other high-performance analog products and DSPs, including the DAC5687 low-noise, 16-bit 500-MSPS dual DAC and the TMS320TCI6482 DSP. Nine of the top 10 base station OEMs use TI technology.

TI Announces Highly Integrated Clock Multiplier Featuring Industry's Best Performance

NewsCenter — Wed, 04 Aug 2004 08:00:00 GMT

Multiple Frequency Outputs, Low Jitter Benefit Consumer Electronics

DALLAS (August 4, 2004) - Leveraging its process technology capabilities, Texas Instruments (TI) (NYSE: TXN) today introduced a highly-integrated clocking integrated circuit (IC) that features three on-chip phase locked loop (PLL) filter components and best-in-class performance. The new clock multiplier´s architecture eliminates the need for external components to support PLL structures, which reduces overall system cost and conserves board space. With very low period jitter and ability to generate multiple clock frequencies, the technology behind the device is well-suited for consumer electronics such as game systems, DVD player/recorders, digital televisions and set-top boxes. (See www.ti.com/sc04169 for more information.)

From a 54-MHz system clock, the CDC5806 generates a video, audio, CPU, USB and portable memory clock out of a single device. Three PLLs generate the various output frequencies from the system clock. On-chip loop filters and internal feedback eliminate the need for external components. Developed in TI's RF SiGe process, the CDC5806 offers low jitter for clock distribution and a very low peak-to-peak period jitter of up to 150 psec.
Future clocks developed in this process will integrate features that help reduce electromagnetic interference (EMI), such as variable Spread Spectrum Clocking (SSC). Variable SSC also enables system designers to fine-tune their designs by allowing them to test various levels of SSC in the system. TI's technology allows integration of such features while maintaining excellent PLL frequency isolation.

Key Features of CDC5806 Include the Following:

Clock input accepts single-ended LVCMOS
Uses a system clock of 54.000 MHz input to generate multiple output frequencies
Low jitter for clock distribution
Operates from single 3.3V supply
Generates the following clocks:
- VIDCLK 74.175824 MHz/54 MHz (buffered)
- AUDCLK 16.9344 MHz/12.288 MHz
- CPUCLK 64 MHz
- USBCLK 48 MHz
- SPCLK 32 MHz
- MSCLK 38.4 MHz/19.2 MHz/12 MHz
PLL filter components integrated
Very low peak-to-peak period jitter characteristic of maximum 150 psec
Industrial temperature range -40 C to 85 C

Available Today

The CDC5806 comes in a 20-pin TSSOP package and is available now from TI and its authorized distributors. Suggested resale pricing is $2.15 each in quantities of 1,000 units.

Information on the complete line of clock solutions from TI is in the Clocks and Timers Selection Guide, available at www.ti.com/clocks.

TI Announces World's First DDR-II PLL Supporting 800MB/s for Registered Memory Modules

NewsCenter — Wed, 16 Jul 2003 08:00:00 GMT

Low Power, Low Jitter Provides Wider Timing Margins for PC, Server, Workstation and Communications Applications

DALLAS (July 16, 2003) - Texas Instruments Incorporated (TI) [NYSE: TXN] announced today the industry´s first Double Data Rate-II (DDR-II) Phase Locked Loop (PLL) for registered memory modules that supports data rates up to 800MB/s. Supporting the industry´s highest frequency, the high-performance, low-skew, low-jitter, zero-delay buffer gives designers wider timing margins necessary in designing high speed DDR Memory Modules found in applications such as PCs, servers, workstations and communications. (See www.ti.com/sc03150.)

High Performance and Ease of Design

The CDCU877 DDR-II PLL is fully compliant with the JEDEC DDR-II standard and distributes a differential-clock input pair to 10 differential pairs of clock outputs and one differential pair feedback-clock output differential pair. Combined with the SN74SSTU32864 DDR-II logic register, this device provides a total chipset solution and facilitates easier part sourcing for DDR-II memory modules.

The SN74SSTU32864 can be configured as a 25-bit 1:1 pinout configuration or a 14-bit 1:2 pinout, allowing users to work with a single part number for multiple DIMM configurations. Output Edge-Control Circuitry is utilized in the device to minimize switching noise in un-terminated lines, improving signal integrity. The device also supports the DDR-II low power, minimizing switching noise into the SDRAM inputs on the DIMM, improving signal integrity and lowering system power consumption.

Pricing and Availability

The CDCU877 is available today and comes in a 52-ball MicroStar Junior^TM BGA and 40-pin MLF package. Planned pricing for the CDCU877 is $3.50 per device in quantities of 1,000.

About TI´s Chipset for Registered DIMMs

TI provides customers high performance complete PLL and Register chip-sets for DDR-I and DDR-II Registered DIMM by leveraging the company´s leadership in analog technology. TI has developed DDR-I PLL and DDR-II Register first in the industry and offers the fastest DDR-II PLL to customers who want to deliver best DDR-II Registered DIMM products to market quickly. For more information, visit www.ti.com/sc/ddrsdram.

Texas Instruments' New Low Phase Noise Clock Synthesizer Reduces Costs, Board Space by 70 Percent

NewsCenter — Wed, 09 Apr 2003 08:00:00 GMT

Ideal for Communications, Instrumentation and Industrial Applications

DALLAS (April 9, 2003) -- Reducing board space by 70 percent, Texas Instruments today announced a new low phase noise clock synthesizer with multiplying, dividing, and jitter cleaning features that optimizes timing performance for board designers. This new integrated chip reduces board costs and the need for numerous discrete components. (See www.ti.com/sc03082 for more information.)

The CDC7005 synchronizes a voltage controlled crystal oscillator (VCXO) with a reference clock and integrates a low noise phase frequency detector, precision charge pump, programmable dividers, operational amplifier, and 1:5 differential clock buffer with dividing options. Ideal for communication, instrumentation, and industrial applications, the device's low phase noise performance is beneficial for many signal chain devices including A/D-D/A converters, serializers, ASICs and digital signal processors (DSPs) requiring precise reference clocking.
The CDC7005 accepts a 3.5 megahertz (MHz) to 180 MHz reference clock and requires a VCXO clock from the range of 10 MHz to 800 MHz to synchronize. By selecting the appropriate VCXO, the device can output up to 800 MHz by multiplying or dividing the reference clock and selecting from a combination of individually programmable divide ratios.
The device offers five low-skew, differential outputs. The CDC7005 offers the flexibility to choose the optimal PLL loop bandwidth even below 10 Hz, providing capability to clean jitter from the incoming reference clock. An integrated operational amplifier may be used for the purpose of optimizing this loop bandwidth with an active filter design. In addition, output phase can programmably be delayed or advanced without the need for external components.

Availability, Packaging and Pricing

TI´s CDC7005 clock synchronizer is available now from TI and its authorized distributors. The device is packaged in a small and thermal optimized 64-pin BGA package. Planned pricing in quantities of 1,000 is $13.80.